The present invention relates generally to a semiconductor devices and, more particularly, to semiconductor devices having PN-junctions with high-aspect ratios. The present invention also relates to the method of manufacturing such semiconductor devices.
Integrated circuit (IC) technology has advanced at a rapid pace over the years. As IC technology advances, the requirements for the basic IC fabrication are becoming more rigorous. The principal factor influencing IC fabrication is the constant demand to reduce the size of the semiconductor devices. Due to this demand, there is a trend toward the use of greater device densities and smaller minimum feature sizes with smaller separations in between.
The basic fabric of the IC technology depends on PN-junctions. The forward bias current of the PN-junction and the PIN (P-region and the N-region separated by an isolation region) of a semiconductor device depend upon the area of the PN-junction. The area of the PN-junction and the forward bias current of the PN-junction are directly proportional to one another. However, the smaller feature size imposed by the present need of the industry, restricts the size of the PN-junction within the semiconductor device. Due to a reduction in size of the PN-junction, the forward bias current is limited, which in turn limits the sense margin of the on-state and the off-state.
In light of the foregoing, there is a need for ICs having PN-junctions and PIN junctions that can withstand a high forward bias current.